Phase shifted full bridge dc dc converter

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Year of fee payment : 4. A DC-to-DC converter has a leading full-bridge inverter and a lagging full-bridge inverter for receiving a DC input and producing respective AC output voltages. A full-wave rectifier circuit rectifies the AC output voltages to produce a rectified output voltage, which is filtered by a current doubling output filter circuit to produce a DC output voltage.

A master phase-shift controller and a slave phase-shift controller respectively provide first and second control signals to the leading full-bridge inverter and third and fourth control signals to the lagging full-bridge inverter to regulate the DC output voltage by changing a phase of the second and fourth control signals with respect to the first and third control signals below a predetermined DC output voltage, and by changing a phase of the third and fourth control signals with respect to the first and second control signals above the predetermined threshold.

This various circuit embodiments described herein relate in general to power converters, and, more specifically, to double phase-shifting full-bridge DC-to-DC power converters having capabilities and advantages of the type described which can be controlled with phase-shifting signals, with a wide-range of zero-voltage-switching ZVS , and with substantially no circulating currents. In the field of power conversion, it is a common practice to convert electrical energy from one DC voltage level to other isolated DC voltage levels using high frequency switching technology.

The use of switching technology dramatically decreases the size of power converters and improves power conversion efficiency. While enjoying the benefits of switching technology, industry is also facing new challenges, including further demands of higher power conversion efficiency, smaller converter size requirements, and lower electromagnetic inference EMI emission requirements that are caused by switched currents and voltages.

In order to improve converter efficiency, reduce the size of converters, and minimize EMI, tremendous efforts have been made to achieve wide-range zero voltage switching ZVS , eliminate circulating currents, perform energy recovery associated with reverse recovery of output diode, and eliminate or clamp voltage ringing of the output diodes. Although a lot of effort has been expended, no comprehensive solution known to the applicant has been achieved that has a wide-range ZVS capability, always operates at maximum duty cycle, fully utilizes magnetic components, minimizes or eliminates circulating current, performs reverse energy recovery, and clamps or eliminates the voltage ringing at output diodes.

Also, what is needed is a control method and topology that can improve peak efficiency and light load efficiency at the same time, without having to switch between PWM and phase-shift control signal modes. The full half-bridge DC-to-DC converter, however, eliminates mode switching between phase-shifting and PWM control signal modes and uses only phase-shifted control signals.

The double phase-shifting full-bridge DC-to-DC converter maintains soft switching over a wider output voltage and load ranges while achieving the same peak efficiency, with improved efficiency at light load. It also maintains soft switching over wider load and output voltage regulation ranges. The two inverters of the double phase-shifting full-bridge DC-to-DC converter can work alone for single full-bridge control or provide two interleaved phase-shifting full-bridges for higher efficiency and higher power applications.

Thus, in accordance with a DC-to-DC converter embodiment described herein, first and second full-bridge inverters receive a DC input, and a full-wave rectifier circuit combines their outputs to produce a DC output. A controller provides control signals to the first and second full-bridge inverters with respective phases dependent upon a DC voltage output. The controller regulates the DC output only by controlling respective phases of the control signals. In accordance with another DC-to-DC converter embodiment, a leading full-bridge inverter and a lagging full-bridge inverter receive a DC input and produce respective AC output voltages.

A full-wave rectifier circuit rectifies the AC output voltages to produce a rectified output PWM voltage, which is filtered by a current doubling output filter circuit to produce a DC output voltage.

A master phase-shift controller and a slave phase-shift controller respectively provide first and second sets of control signals to the leading full-bridge inverters and third and fourth sets of control signals to the leading full-bridge inverter. The master and slave phase-shift controllers regulate the DC output voltage by changing a phase of the second and fourth sets of control signals with respect to the first and third sets of control signals below a predetermined DC output voltage, and by changing a phase of the third and fourth sets of control signals with respect to the first and second sets of control signals above the predetermined DC output voltage.

In accordance with yet another DC-to-DC converter embodiment, a first full-bridge inverter has first and second current paths for producing a first AC output voltage in response to a DC input voltage.

A second full-bridge inverter has third and fourth current paths for producing a second AC output voltage in response to the DC input voltage. A full-wave rectifier circuit receives the first and second AC output voltages to produce a rectified PWM output voltage that is filtered by a current doubling output filter circuit to produce a DC output voltage.

A first phase-shift controller receives the DC output voltage as a feedback signal and provides a set of first control signals to the first current path and a set of second control signals to the second current path.

A second phase-shift controller receives the DC output voltage feedback signal from first phase-shift controller and provides a set of third control signals to the third current path and a set of fourth control signals to the fourth current path. To regulate the DC output voltage, when the DC output voltage is below a predetermined threshold voltage the first phase-shift controller controls a phase of the second set of control signals with respect to a phase of the first set of control signals in proportion to the DC output voltage.

When the DC output voltage is above the predetermined threshold voltage the first phase-shift controller maintains the second phase to be degrees out of phase with the first phase. When the DC output voltage is below the predetermined threshold voltage the second phase-shift controller controls a phase of the third and fourth sets of control signals to be substantially the same as the first and second phases. When the DC output voltage is above the predetermined threshold voltage the second phase-shift controller controls a phase of the third and fourth set of control signals in proportion to the DC output voltage with respect to the first and second phases.

This eliminates circulating power, a barrier to improving the peak efficiency of a full-bridge converter. This topology and control allows part of the circuit to be turned off at light load, decreases circuit switching loss, and boosts the efficiency of the circuit. If the two controller circuits are connected in master and slave configuration, the resulting controller can control a single phase-shifting full-bridge or two interleaved phase-shifting full-bridges. In the various figures of the drawing, like reference numbers are used to denote like or similar parts.

The double phase-shifting full-bridge DC-to-DC converter 10 includes first and second full-bridge inverters 12 and 14 , the first full-bridge inverter 12 sometimes being referred herein to as a leading full-bridge inverter or as a master full-bridge inverter, and the second full-bridge inverter 14 sometimes being referred to herein as a lagging full-bridge inverter or a slave full-bridge inverter, described below in detail.

The leading and lagging full-bridge inverters 12 and 14 each have four switching transistors, Q 1 -Q 4 and Q 5 -Q 8 , respectively, shown in FIG. It should be noted that although two separate phase-shift controllers 16 and 18 are shown, denoted as master and slave phase-shift controllers, the control functions may be incorporated into a single unit, represented by the dotted line box The leading and lagging full-bridge inverters 12 and 14 develop respective AC output voltages on lines 26 and 28 , which are rectified and filtered by a full-wave rectifier circuit and current doubling output filter The DC output voltage, Vo, is developed on output line 32 , which is sensed and fed back to the master and slave phase-shift controllers 16 and 18 to regulate the DC output voltage, Vo, as described below in detail.

Another control scheme not shown is to provide the DC output voltage, Vo, to the master phase-shift controller 16 as a feedback signal, with the master phase-shift controller 16 providing a compensator output and synchronous signal to the slave phase-shift controller 18 for regulation of the DC output voltage, the goal being to develop the control waveform sets described below.

Although the power switches herein are described as MOSFET devices, IGBTs isolated gate bipolar transistors , or other types of semiconductor switching devices may be equally advantageously employed.

A pair of capacitive elements Cq 1 and Cq 2 , whose values include the parasitic capacitance of the power switches Q 1 and Q 2 , as well as any external capacitances that are connected across the power switches Q 1 and Q 2 , respectively. Likewise, the diodes Dq 3 and Dq 4 are the body diodes of the power switches Q 3 and Q 4 , respectively, and the capacitive elements Cq 3 and Cq 4 have values which include the parasitic capacitance of power switches Q 3 and Q 4 , as well as any external capacitances that are connected across the power switches Q 3 and Q 4.

For the system, the excessive K i will cause instability and the increase of overshoot. Here, K i is set as Finally, K d should be increased slowly to reduce the adjustment time. But K d can cause oscillation.

The structure diagram of the fuzzy controller is shown in Fig. Because ANF controller designed in the later stage requires multiple input and single output, Sugeno type is adopted. In the fuzzy PID controller, the deviation E s and the deviation change rate EC s will be input into the fuzzy controller. The purpose of fuzzification is to determine the fuzzy quantization factor and membership function of input E s and EC s.

According to the simulation results showed in Fig. So, the corresponding values are as follows:. When E s is large, to quickly reduce the deviation, it is necessary to increase K p and reduce K d. At the same time, K i is set as zero to eliminate the influence of the integral term. In this case, the large overshoot will be avoided in the regulation process. When E s is medium, the main task is to avoid the system shaking.

So, a slightly larger K d is preferable, while reducing K p to avoid overshoot. When E s is small, it is necessary to increase K p and K i appropriately to reduce the adjustment time. At the same time, K d should be inversely correlated with EC s to avoid oscillation 25 — According to the above principles, the fuzzy control rules are obtained.

The output surfaces of the proportion, the integral and differential coefficients on the domain, respectively, are shown in Fig. Due the fuzzy control rules of fuzzy PID are fixed, the fuzzy PID control strategy cannot adjust the initial PID parameters accurately, so it is not satisfied the expectation of the system. Therefore, an ANF controller has been applied to optimize the closed-loop system.

According to the simulation result shown in Figs. So, the simulation data from fuzzy PID controller can be used as sample data. There are data sets as sample data to train the Sugeno fuzzy controller generated in the progress of designing of Sugeno Fuzyy PID controller. As one of neural network self-learning algorithm, back propagation algorithm is utilized to generate ANF PID controller.

There are five layers of the ANF control network shown in Fig. The meanings and functions of each layer are as follows:. The first layer is the input layer which is composed of two neural nodes. The layer is responsible for transmitting E s and EC s to the next layer. The second layer, composed of two groups of neural nodes, describes the membership function of the fuzzy input.

The neural nodes represent the fuzzy language variables of E s and EC s respectively. This layer is responsible for obscuring the input. The third layer is the ANF control rule layer, which is composed of 49 neural nodes. Each node represents a fuzzy rule.

The fourth layer is the membership function of the fuzzy output. The layer is also composed of 49 neural nodes corresponding to the 49 control rules in the third layer.

In the layer, each node represents the weight of the corresponding rules. The fifth layer is the output layer. In the layer, each control rule is linearly combined to obtain the fuzzy output. Backpropa algorithm was used to optimize the weight in fourth layer. To achieve the expected result, the error tolerance value is set as 0.

After 10, iterations, the error is reduced to 0. Compare with Fig. For E s and EC s , because of the difference in the weight, the shapes of membership functions are also different in adaptive neural fuzzy PID controller.

For adaptive neural fuzzy PID controller, the output surfaces of the proportion, the integral and differential coefficients on the domain, respectively, are shown in Fig. The fuzzy control rules adjust timely based on the real states of system.

So, the control effect could meet the expectation of the system. Under these strategies, the response of closed-loop system could be optimized. The output voltages of the systems for the small-signal model are shown in Fig. Compared with Fig. For the three control strategies, the optimization effect of PID control is the weakest. To compare the effectivity of the methods, the optimization rate of overshoot G is defined as.

According to the response curves and characteristic values shown in Fig. From simulation results of the small-signal model, the ANF PID controller is more adaptive to optimize the control system than the two other methods. The simulation model of the circuit system is shown in Fig. Similar with small-signal model, the over-shoot and optimization rate of the output voltage are greatly improved when closed-loop controller is applied in circuit model.

This result is different from that of the small-signal model. The may reason for the differences is that the circuit model is a kind of physical model in which the components exist inherent response time. The excessive overshoot will seriously affect charging system of electric vehicles performance and shorten its life. The stabilities, responding speed and overshoot of the system are regulated by adjusting the factors of the control strategy. From the results of the simulations for small-signal model and circuit model, the effect of ANF PID control in the three closed-loop control system is optimal.

In a conclusion, the ANF PID controller can be applied to the electric vehicle battery charging technology, which will improve the anti-interference performance of the circuit and enhance the stability of the charging process. But adaptive neural fuzzy controller adopted in this paper needs more complicated data training and the hardware of this control strategy is difficult to be realized.

These are our next research. Fortunately, dynamic adjustment of circuit parameters through machine learning method to achieve better control effect should be a more meaningful direction in the development of control. In the future, the methods and results of simulation may be used to the practical circuits to design an efficient and stable electric vehicle battery charger.

Conceptualization, Y. All authors have read and agreed to the published version of the manuscript.